Parity checking circuits verify the correct operation of a data processing system by providing a summation check in which the bits in a group are added and the sum checked against a single previously computed parity digit. In other words, the checking circuit tests whether the number of "one" bits in the group is even or odd. In a typical operation, a data byte having eight bits has an additional ninth bit appended to it for the parity check. If odd parity has been preselected, the sum of the nine bits must be odd. Thus, if the eight bits sum to zero, two, four, six or eight, the parity bit will be a one so that the sum of the nine bits is odd. If the eight bits sum to one, three, five or seven, the parity bit will be a zero. In this manner, errors in the storage or transmission of data may be detected.
Typical prior art parity circuits use eight, two-input Exclusive-OR gates for processing nine bits (one byte and an associate parity bit). An improved parity checking circuit is disclosed in U.S. Pat. No. 4,749,887, entitled, "3-Input Exclusive-OR Gate Circuit", by I. Sanwo, et al. The '887 patent discloses a three input Exclusive OR gate for use in a parity checking circuit. The '887 patent is a significant improvement over prior art circuits by its reduced gate count and improved performance. One feature of the '887 patent is a number of NMOS/PMOS transistor "pairs". Such pairs require jumper wire connections which may have node capacitance and require additional layout space in an integrated circuit implementation.